Transistor sizing for radiation hardening

@article{Zhou2004TransistorSF,
  title={Transistor sizing for radiation hardening},
  author={Quming Zhou and Kartik Mohanram},
  journal={2004 IEEE International Reliability Physics Symposium. Proceedings},
  year={2004},
  pages={310-315}
}
This paper presents an efficient and accurate numerical analysis technique to simulate single event upsets (SEUs) in logic circuits. Experimental results that show the method is accurate to within 10% of the results obtained using SPICE are provided. The proposed method is used to study the ability of a CMOS gate to tolerate SEUs as a function of injected charge and transistor sizing (aspect ratio W/L). A novel radiation hardening technique to calculate the minimum transistor size required to… CONTINUE READING
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