Transistor sizing and folding techniques for radiation hardening


The efficiency of transistor sizing and folding techniques to mitigate SET in CMOS circuits is evaluated using circuit and device simulations. According to the LET of the ionizing particle, the SET can be more or less filtered by these methods. Based on the results of the circuit and device simulations, a novel technique able to reduce the SET effect is… (More)

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@article{Kastensmidt2009TransistorSA, title={Transistor sizing and folding techniques for radiation hardening}, author={F. Lima Kastensmidt and Thiago Brand{\~a}o de Assis and Igor R B Ribeiro and G. I. Wirth and Lucas Brusamarello and Rog'erio Reis}, journal={2009 European Conference on Radiation and Its Effects on Components and Systems}, year={2009}, pages={512-519} }