Transistor-level layout of high-density regular circuits

@inproceedings{Lin2009TransistorlevelLO,
  title={Transistor-level layout of high-density regular circuits},
  author={Yi-Wei Lin and Malgorzata Marek-Sadowska and Wojciech Maly},
  booktitle={ISPD},
  year={2009}
}
In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate transistor-array-based layout. Interconnects on all metal layers are uni-directional and can be manufactured by an OPC-free process [4]. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of… CONTINUE READING

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