Traffic-aware power-gating scheme for Network-on-Chip routers

@article{Nasirian2016TrafficawarePS,
  title={Traffic-aware power-gating scheme for Network-on-Chip routers},
  author={Nasim Nasirian and Reza Soosahabi and Magdy A. Bayoumi},
  journal={2016 IEEE Dallas Circuits and Systems Conference (DCAS)},
  year={2016},
  pages={1-4}
}
Network-on-Chip technology has become very popular in the recent decade to address the scalability issue in multi-core processors. Developing the inter-connection network improves the performance of multi-core systems at the cost of additional power and design complexity. Power-gating of router buffers as the most power consuming part of Network-on-Chip has been proposed recently to reduce the static power consumption. However, power-gating has its own shortcomings in terms of delay and power… CONTINUE READING