Trading Accuracy for Power with an Underdesigned Multiplier Architecture

  title={Trading Accuracy for Power with an Underdesigned Multiplier Architecture},
  author={Parag Kulkarni and Puneet Gupta and Milos D. Ercegovac},
  journal={2011 24th Internatioal Conference on VLSI Design},
We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 building block. Our inaccurate multipliers achieve an average power saving of 31.78% ? 45.4% over corresponding accurate multiplier designs, for an average error of 1.39%?3.32%. Using image filtering and JPEG compression as sample applications we show that our architecture can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent… CONTINUE READING
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Estimating adders for a low density parity check decoder

  • B. J. Phillips, D. R. Kelly, B. W. Ng
  • F. T. Luk, Ed., vol. 6313, no. 1. SPIE, 2006, p…
  • 2006
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