Tradeoffs between settling time and jitter in phase locked loops

@article{Paliwal2013TradeoffsBS,
  title={Tradeoffs between settling time and jitter in phase locked loops},
  author={Pallavi Paliwal and Priyank Laad and Mohanrao Sattineni and Shalabh Gupta},
  journal={2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)},
  year={2013},
  pages={746-749}
}
In most phase locked loops, an obvious trade-off exists between settling time, output jitter and power consumption. However, dependence of jitter on settling time is commonly ignored while evaluating PLL designs. In this paper, the tradeoffs between settling time and jitter is analyzed for different types of All-Digital PLLs (ADPLLs). Based on these analytical results, a Figure of Merit (FoM) for evaluating PLLs, which takes settling time into consideration, is suggested. Survey carried out… CONTINUE READING

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References

Publications referenced by this paper.
SHOWING 1-3 OF 3 REFERENCES

A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs

  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2005
VIEW 3 EXCERPTS
HIGHLY INFLUENTIAL

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