Modeling and simulation are becoming extensively used in embedded and Real-Time Systems (RTSs) development throughout the development life-cycle, from the system-level design space exploration to the fine grained time analysis and evaluation of the system and even its components performance. At the core of these systems lies the processor which has been also the center of attention for most of the modeling and simulation efforts related to RTS simulation. Although the temporal accuracy of such models and simulators is of critical importance for Real-Time (RT) applications, it is not yet mature how this accuracy can be expressed and assessed to enable correct design decisions making during the different development phases to satisfy the RTS requirements. In this paper, we present a robust methodology for temporal accuracy assessment of any processor's simulator through its bus transactions logged on a cycle accurate basis. The proposed methodology suggests projection of RTS requirements on models and simulators to extract RT-related requirements. The proposed temporal accuracy assessment approach is introduced and justified via a set of preliminary experiments.