Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures

Abstract

In this paper, we consider two Network-on-Chip (NoC) architectures used within commercially available many-core systems, namely Tilera TILE64 which implements flow regulation within routers and KalRay MPPA 256 which implements flow regulation in source nodes. The Worst-Case Traversal Time (WCTT) on the NoC has to be bounded for real-time applications, and… (More)
DOI: 10.1109/WFCS.2016.7496535

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