Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware

Abstract

Formal verification is increasingly important in asynchronous circuit design, since the lack of a global synchronizing clock makes errors due to concurrency (e.g., deadlocks) virtually impossible to detect by means of conventional methods such as simulation. This paper presents a hierarchical approach to asynchronous systems verification using CSP and its… (More)
DOI: 10.1016/j.entcs.2005.04.014

Topics

9 Figures and Tables

Cite this paper

@article{Wang2005TowardsAU, title={Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware}, author={Xu Wang and Marta Z. Kwiatkowska and Georgios K. Theodoropoulos and Qianyi Zhang}, journal={Electr. Notes Theor. Comput. Sci.}, year={2005}, volume={128}, pages={231-246} }