Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers

  title={Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers},
  author={Dina Kamel and Guerric de Streel and Santos Merino Del Pozo and Kashif Nawaz and François-Xavier Standaert and Denis Flandre and David Bol},
With the exploding number of connected objects and sensitive applications, security against side-channel attacks becomes critical in low-cost and low-power IoT applications. For this purpose, established mathematical countermeasures such as masking and shuffling always require a minimum amount of noise in the adversary’s measurements, that may not be guaranteed by default because of good measurement setups and powerful signal processing. In this paper, we propose to improve the protection of… 

Fluctuating Power Logic: SCA Protection by $V_{DD}$ Randomization at the Cell-level

A novel cell-level side channel countermeasure fluctuating power logic (FPL) is proposed, which diffuses the correlation between the real power consumption and the fixed data transitions by employing a cascade voltage logic.

EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation

An efficient countermeasure technique against the electromagnetic (EM) side-channel attacks is proposed that is applied to switched-capacitor (SC) dc–dc converters and is based on amplitude modulation of the load signal by the converter capacitance that acts as a carrier.

Design and Evaluation of Fluctuating Power Logic to Mitigate Power Analysis at the Cell Level

  • Fan ZhangBolin Yang K. Ren
  • Business
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2021
A novel cell-level power-analysis countermeasure, named fluctuating power logic (FPL), which diffuses the correlation between the real power consumption and the fixed data transitions by employing a cascade voltage logic.

Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices

  • R. JevticM. YlitolvaL. Koskinen
  • Engineering, Computer Science
    2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
  • 2018
This work analyzes the most common converter topologies and proposes reconfigurable switched-capacitor cell for the efficient implementation in CMOS technology, showing that power and time entropy of the proposed cell are increased significantly when compared to the commonly used DC-DC converter cell.

Practical Evaluation of FSE 2016 Customized Encoding Countermeasure

Under simulated setting, it can be verified that customized encoding shows strong security properties under proper assumption of leakage estimation and noise variance and in practical setting, the general observation is that the side-channel leakage will mostly be present even if the encoding scheme is applied.

How (not) to Use Welch's T-test in Side-Channel Security Evaluations

It is shown that even in a simple case study that seems best suited for the TVLA methodology, detection with Welch’s T-test can be totally disconnected from the actual security level of an implementation.



Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks

Circuit level techniques are proposed in this paper as a countermeasure against side-channel attacks where the active stages are reshuffled with so called converter-reshuffling to insert random spikes in the power consumption profile.

Secure AES engine with a local switched-capacitor current equalizer

  • Carlos TokunagaD. Blaauw
  • Computer Science, Mathematics
    2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
  • 2009
Differential power analysis (DPA) is one of the most common side-channel attacks because of its simplicity and effectiveness and performs a statistical analysis of supply-current measurements and either the plaintext or ciphertext to disclose the secret key.

On-Chip Voltage Regulator Protecting Against Power Analysis Attacks

The on-chip voltage regulator proposed in this paper has been specifically developed for smart cards. Its purpose is to protect the supplied system against power analysis attacks. It allows to

Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure

  • Karthik BaddamMark Zwolinski
  • Computer Science
    20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
  • 2007
The authors propose an alternative technique which only varies the supply voltage randomly, which significantly weakens the DPA attack by reducing the correlation of power to processed data.

A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices

This paper provides the first comprehensive treatment of variability issues for side-channel attacks and defines the perceived information to quantify this context, which generalizes the notion of mutual information with possibly degraded leakage models.

Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box

The important question whether dual-rail logic styles remain a promising approach for reducing the side-channel information leakages in front of technology scaling, as hardware constraints such as balanced routing may become increasingly challenging to fulfill, as circuit sizes tend towards the nanometer scale is raised.

Soft Analytical Side-Channel Attacks

A new approach to side-channel key recovery is introduced, that combines the low time/memory complexity and noise tolerance of standard (divide and conquer) differential power analysis with the optimal data complexity of algebraic side- channel attacks.

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags

The AES algorithm can fit into this micro Watt power budget by combining ultra-low-voltage implementations with a proper selection of the process flavor in a low-cost nanometer CMOS technology, and this approach only requires slight modifications to the standard EDA tool flow, without incurring the engineering costs of architecture optimizations.

Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators

This paper explores the feasibility of using an on-chip low dropout regulator (LDO) as a countermeasure to power attack of low-power and compact encryption engine and shows that LDO can increase power attack resistance of the compact AES by >800X.

A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks (extended version)

A framework for the analysis of cryptographic implementations that includes a theoretical model and an application methodology, based on commonly accepted hypotheses about side-channels, that allows quantifying the effect of practically relevant leakage functions with a combination of information theoretic and security metrics.