Corpus ID: 7077400

Towards Reconfigurable Cache Memory for a Multithreaded Processor

@inproceedings{Ogasawara2006TowardsRC,
  title={Towards Reconfigurable Cache Memory for a Multithreaded Processor},
  author={Yoshiyasu Ogasawara and Ippei Tate and Satoshi Watanabe and M. Sato and Koichi Sasada and Kaname Uchikura and Kazunari Asano and M. Namiki and H. Nakajo},
  booktitle={PDPTA},
  year={2006}
}
Recently reconfigurable devices such as FPGA have improved performance (gate speed and the number of gates) and reconfiguration time. Today, a reconfigurable device can integrate a largescale processor and complex hard-wired logic. System designers found that they need a highperformance processor for their reconfigurable device based systems. To improve processor performance, a multithreaded architecture has been introduced; however, performance decreases drastically because of cache misses for… Expand
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