Corpus ID: 7077400

Towards Reconfigurable Cache Memory for a Multithreaded Processor

  title={Towards Reconfigurable Cache Memory for a Multithreaded Processor},
  author={Yoshiyasu Ogasawara and Ippei Tate and Satoshi Watanabe and Mikiko Sato and Koichi Sasada and Kaname Uchikura and Kazunari Asano and Mitaro Namiki and Hironori Nakajo},
Recently reconfigurable devices such as FPGA have improved performance (gate speed and the number of gates) and reconfiguration time. Today, a reconfigurable device can integrate a largescale processor and complex hard-wired logic. System designers found that they need a highperformance processor for their reconfigurable device based systems. To improve processor performance, a multithreaded architecture has been introduced; however, performance decreases drastically because of cache misses for… Expand
An Effective Replacement Strategy of Cache Memory for an SMT Processor
An effective replacement strategy in which conflicts miss ratio among threads is controlled by limiting the range of replaceable cache blocks is proposed and designed in order to overcome the problem on cache memory of an SMT processor. Expand
Adaptive Cache Infrastructure: Supporting Dynamic Program Changes following Dynamic Program Behavior
An infrastructure for fitting cache accesses to a program’s requirements for a distinct phase is proposed, with the memory access behavior being most important and caches being a very big subset of them. Expand


A reconfigurable multi-function computing cache architecture
This paper presents a cache architecture to convert a cache into a computing unit for either of the following two structured computations, FIR and DCT/IDCT, and shows that the reconfigurable module improves the execution time of applications with a large number of data elements by a large factor. Expand
Reconfigurable caches and their application to media processing
A new reconfigurable cache design is proposed that enables the cache SRAM arrays to be dynamically divided into multiple partitions that can be used for different processor activities. Expand
Fast context switching by hierarchical task allocation and reconfigurable cache
  • Kiyofumi Tanaka
  • Computer Science
  • Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
  • 2003
The general-purpose RISC processor architecture is extended and a new RISC core is developed which can be used to implement the seamless task switching, fast response to interrupt requests, and the reconfigurable caches, for supporting real-time processing in a multi-tasking environment. Expand
Dynamic Partitioning of Shared Cache Memory
The results show that smart cache management and scheduling is essential to achieve high performance with shared cache memory and can improve the total IPC significantly over the standard least recently used (LRU) replacement policy. Expand
Simultaneous multithreading: Maximizing on-chip parallelism
Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multi-threading, and is an attractive alternative to single-chip multiprocessors. Expand
Hyper-Threading Technology Architecture and MIcroarchitecture
The Hyper-Threading Technology architecture is described, and the microarchitecture details of Intel's first implementation on the Intel Xeon processor family are discussed, which is an important addition to Intel's enterprise product line and will be integrated into a wide variety of products. Expand
The SPLASH-2 programs: characterization and methodological considerations
This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality. Expand
Computer Architecture - A Quantitative Approach, 5th Edition
A quantitative approach to computer architecture a quantitative approach 5th edition computer architecture quantitative approach solution manual computer Architecture quantitative approach solutions manual computer architecture an quantitative approach 3rd editionComputer architecture, fifth edition. Expand
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation
Implementation and Evaluation of a Thread Library for Multithreaded Architecture