Top-Down Designs of Instruction Systolic Arrays for Polynomial Interpolation and Evaluation

Abstract

This paper describes the application of a new parallel architecture-instrnctrction systolic array ( ISA)-for the interpolation and evaluation of polynomials using a linear array of processors. It also demonstrates a systematic top-down design of instruction systolic arrays. The periods of the resulting algorithms are O(n) for interpolation and o( 1) for… (More)
DOI: 10.1016/0743-7315(89)90014-2

Topics

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