Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications

@article{Fricke2017ToolFF,
  title={Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications},
  author={Florian Fricke and Andr{\'e} Werner and Michael H{\"u}bner},
  journal={2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)},
  year={2017},
  pages={1-2}
}
The toolflow presented in this demo was created to generate CGRA overlay architectures from either algorithm definitions (mainly for evaluation) or from a simple definition format. The output of the toolchain is always the complete definition of the hardware in VHDL and supplemental files providing information regarding the configuration and the interfaces of the created hardware. In the demo, we show the complete process from the selection of an algorithm over the creation of the hardware… CONTINUE READING