Title: Manufacturing Yield-driven Layout Scaling of Vlsi Ics

Abstract

This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design which is optimal from the manufacturing yield point of view. It allows also to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well.

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Cite this paper

@inproceedings{Pleskacz1998TitleMY, title={Title: Manufacturing Yield-driven Layout Scaling of Vlsi Ics}, author={Witold A. Pleskacz}, year={1998} }