Timing-driven placement for FPGAs

  title={Timing-driven placement for FPGAs},
  author={Alexander Marquardt and Vaughn Betz and Jonathan Rose},
In this paper we introduce a new Simulated Annealing-based timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a novel method of determining source-sink connection delays during placement. Second, we introduce a new cost function that trades off between wire-use and critical path delay, resulting in significant reductions in critical path delay without significant increases in wire-use. Finally, we combine connection-based and path… CONTINUE READING
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Architecture and CAD for Speed and Area Optimization of FPGAs

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Performance-Driven Simultaneous Place and Route for Row-Based FPGAs

31st Design Automation Conference • 1994
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