Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing

@article{Moiseev2015TimingconstrainedPM,
  title={Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing},
  author={Konstantin Moiseev and Shmuel Wimer and Avinoam Kolodny},
  journal={Integration},
  year={2015},
  volume={48},
  pages={116-128}
}
Reduction of interconnect delay and interconnect power has become a primary design challenge in recent CMOS technology generations. Spacing between wires can be modified so that line-to-line capacitances will be optimized for minimal power under timing constraints. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing that minimizes the total dynamic power dissipation caused by an interconnect, while maximum delay constraints are satisfied. A multi… CONTINUE READING
BETA

References

Publications referenced by this paper.

Similar Papers

Loading similar papers…