Timing-aware power-optimal ordering of signals

@article{Moiseev2008TimingawarePO,
  title={Timing-aware power-optimal ordering of signals},
  author={K. Moiseev and A. Kolodny and S. Wimer},
  journal={ACM Trans. Design Autom. Electr. Syst.},
  year={2008},
  volume={13},
  pages={65:1-65:17}
}
A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that cross-capacitances between wires are optimally shared. The existence of a unique power-optimal wire order within a bundle is proven, and a method to construct this order is derived. The optimal order of wires depends only on the activity factors of the underlying signals; hence, it can be performed… Expand
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