• Corpus ID: 63205185

Timing Verification of Application-Specific Integrated Circuits (Asics)

  title={Timing Verification of Application-Specific Integrated Circuits (Asics)},
  author={Farzad Nekoogar},
high-speed designs, timing analysis is critical to success. This is the first book to focus exclusively on these crucial timing issues, with special emphasis on timing verification of... 

Improved Static Timing Path Analyzer for DSCH Tool

The theory of static timing analysis (STA) is described and its design and implementation in DSCH tool, a subpart of microwind chip design EDA tool, specialized in schematic digital circuit design that also supports timing analysis.


The design of a generalized reusable core that can perform built-in self-test for logic cores and interconnects, when integrated into a SoC design, has been proposed in this thesis and can bring about considerable reduction in the verification time.

Testing for Transistor Aging

On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing for future systems.

Diagnostic Test Pattern Generation and Fault Simulation for Stuck-at and Transition Faults

In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good

Wire Delay Models for Global Placement of ASICs

A new model for the propagation delay between two logic gates for timing-driven global placement is proposed, which is 31% more accurate than the current state-of-the-art model and has comparable computational complexity.

Symbolic Verification of Complex Real-Time Systems with Clock-Restriction Diagram

A new CRD-based representation, cascade CRD, is designed which has given enough performance enhancement to successfully verifying several implementations of the web-camera.

3 Megapixel Camera Signal Processor for Mobile Camera Applications

In this work, the presented SoC architecture of the camera signal processor (CSP) provides not only image signal processing functions but also various actuator interfaces and an adaptive data synchronization method using the glitch-free clock switching technique.

Dynamisch und partiell rekonfigurierbare Hardwarearchitektur mit adaptivem hardwaregestützten Routing zur Laufzeit

Zu den neuen Features dieser Architektur gehoren Multikontextfahigkeiten, multigranulare Datentypen, programmierbare Ein-/Ausgabelogik and adaptives Routing zur Laufzeit.