Modern microprocessor pipelines experience timing uncertainties due to manufacturing process variations, thermal variations, supply voltage droop and data-dependent path delays. This leads to power and/or performance inefficiencies in current timing guard banding methods especially when pipeline stages are operating well under their critical path timing constraints due to the temporal characteristics of input data. In this paper, we propose a novel adaptive pipeline design that automatically adjusts to timing variations, thus reducing/eliminating the need for design guard banding. Each pipeline stage is equipped with an activity completion sensor that determines switching activity completion in the respective pipeline stage with a very high probability of correctness. The switching activity completion detection is used to trigger handoff of data from one pipeline stage to another. The pipeline is equipped with low overhead back-up error resilient circuits to handle incorrect (but infrequent) completion sensing and continue forward progress. Such a scheme enables time lending between pipeline stages, thus allowing correct pipeline computations at a lower voltage/higher clock frequency as compared to fully synchronous designs. Simulations and layout generated results from extracted net lists of pipelined arithmetic designs show 32.52% improvement in throughput at same supply voltage or 18% lesser power for the same throughput over conventional fully synchronous design incorporating worst-case safety margins.