Timing-Error-Tolerant Network-on-Chip Design Methodology

  title={Timing-Error-Tolerant Network-on-Chip Design Methodology},
  author={Rutuparna Tamhankar and Srinivasan Murali and Stergios Stergiou and Antonio Pullini and Federico Angiolini and Luca Benini and Giovanni De Micheli},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
With technology scaling, the wire delay as a fraction of the total delay is increasing, and the communication architecture is becoming a major bottleneck for system performance in systems on chip (SoCs). A communication-centric design paradigm, networks on chip (NoCs), has been proposed recently to address the communication issues of SoCs. As the geometries of devices approach the physical limits of operation, NoCs will be susceptible to various noise sources such as crosstalk, coupling noise… CONTINUE READING
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