Timing Driven Placement Recon guration for Fault Tolerance and Yield Enhancement in FPGAs


The architectural regularity of FPGAs provides an inherent redundancy which can be exploited for fault tolerance and yield enhancement. In this paper we examine the problem of recon guring the placement of a circuit on an FPGA to tolerate a given fault pattern in the array of CLBs. The primary objective of the placement recon guration is to minimize timing… (More)


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