Timing-Driven Placement

  title={Timing-Driven Placement},
  author={David Z. Pan and Bill Halpin and Haoxing Ren},
  booktitle={Handbook of Algorithms for Physical Design Automation},
The placement algorithms presented in the previous chapters mostly focus on minimizing the total wirelength (TWL). Timing-driven placement (TDP) is designed specifically targeting wires on timing critical paths. It shall be noted that a cell is usually connected with two or more cells. Making some targeted nets shorter during placement may sacrifice the wirelengths of other nets that are connected through common cells. While the delay on critical paths decreases, other paths may become critical… Expand
Two Approaches for Timing-Driven Placement by Lagrangian Relaxation
  • Gang Wu, C. Chu
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2017
The proposed Lagrangian relaxation (LR)-based algorithms to optimize both circuit performance and total wirelength at the global placement stage are able to achieve significant improvements on circuit performance compared with a commercial wirelength-driven placement flow and a commercial asynchronous TDP flow. Expand
Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits
A physical mapping tool for quantum circuits is presented, which generates the optimal universal logic block (ULB) that can, on average, perform any logical fault-tolerant quantum operations with the minimum latency. Expand
A Performance Driven Placement System Using an Integrated Timing Analysis Engine


Detailed placement with net length constraints
  • B. Halpin, N. Sehgal, C. Chen
  • Engineering, Computer Science
  • The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.
  • 2003
A new NLC global placement rebalancing method and two detailed placement algorithms that work in conjunction with the recursive bisection net-constrained global placer (Alpert et al., 2001) are presented. Expand
Timing-driven placement for FPGAs
A new Simulated Annealing-based timing-driven placement algorithm for FPGAs is introduced that employs a novel method of determining source-sink connection delays during placement and introduces a new cost function that trades off between wire-use and critical path delay, resulting in significant reductions incritical path delay without significant increases in wire- use. Expand
Timing Driven Placement for Large Standard Cell Circuits
The timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells. Expand
Min-max placement for large-scale timing optimization
This work introduces a novel minimization of maximal path delay that improves upon previously known algorithms for timing-driven placement and has provable properties and are fast in practice. Expand
SPEED: fast and efficient timing driven placement
A timing driven placement approach for very large circuits is described, and results of benchmark circuits with up to 25,000 cells show an excellent quality in terms of maximum path delay and total area after final routing. Expand
A new LP based incremental timing driven placement for high performance designs
A timing aware spreading method to preserve timing in legalization for high performance designs and has been tested on a set of 65nm industry circuits from a multi-GHz microprocessor, and shown to achieve much improved timing on hand-tuned circuits. Expand
Sensitivity guided net weighting for placement-driven synthesis
  • Haoxing Ren, D. Pan, D. Kung
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2005
A comprehensive analysis of the wirelength, slack, and FOM sensitivities to the net weight, and a new net weighting scheme based on those sensitivities are proposed, which shows promising results for both stand-alone TDP and physical synthesis afterwards. Expand
Timing Influenced Layout Design
This work presents a new approach to the automatic layout design for VLSI chips which incorporates timing information to influence the placement and wiring processes, and adds a third phase of timing to the hierarchy without affecting the computational complexity of the basic algorithm. Expand
A novel net weighting algorithm for timing-driven placement
  • Tim Kong
  • Computer Science
  • IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.
  • 2002
This paper presents a novel net weighting algorithm based on the concept of path-counting, and applies it in a timing-driven FPGA placement application, and theoretically this is the first ever known accurate, all-path counting algorithm. Expand
Large-scale circuit placement
This tutorial summarizes results from recent optimality and scalability studies of existing placement tools, and highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization. Expand