Timing Diagrams: Formalization and Algorithmic Verification

  title={Timing Diagrams: Formalization and Algorithmic Verification},
  author={Kathi Fisler},
  journal={Journal of Logic, Language and Information},
Timing diagrams are popular in hardware design. They have been formalized for use in reasoning tasks, such as computer-aided veriication. These eeorts have largely treated timing diagrams as interfaces to established notations for which veriication is decidable; this has restricted timing diagrams to expressing only regular language properties. This paper presents a timing diagram logic capable of expressing certain context-free and context-sensitive properties. It shows that veriication is… CONTINUE READING
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