Timing Characterization of Dual-edge Triggered Flip-flops

Abstract

A novel timing characterization for dual-edge triggered flip-flops is presented in this paper. This characterization takes into account the real overhead taken from the clock cycle by the flip-flops. Our study shows the correctness of this new metrics when compared against data-to-output delay. 
DOI: 10.1109/ICCD.2001.955087

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