Timing-Aware Power-Noise Reduction in Placement


We describe a placement-level decoupling capacitance (decap) insertion technique whose objective is to reduce power noise, taking into account circuit timing. Our approach consists of prediction and correction steps. Before placement, we estimate the power noise of each cell considering switching frequency of cells that, after placement, will most likely be in the neighborhood. If a frequently switching cell has neighbors that switch infrequently, it is unlikely that this cell will suffer from a power-noise problem. Based on the cell power-noise estimation, we add decap padding to each cell. Then, we invoke a standard cell placement tool and perform power grid analysis. We eliminate the power grid noise by gate sizing. Our technique can allocate decaps to improve power noise, power consumption, and timing. We propose two gate-sizing algorithms. The first one uses a sequence of linear programs (SLP) formulation, and the second one uses a budgeting-based heuristic algorithm. The SLP algorithm can produce better power-noise results than the heuristic, at the expense of runtime. Experimental results show that our techniques can effectively reduce power noise and still meet timing constraints

DOI: 10.1109/TCAD.2006.883917

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@article{Yeh2007TimingAwarePR, title={Timing-Aware Power-Noise Reduction in Placement}, author={Chao-Yang Yeh and Malgorzata Marek-Sadowska}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, year={2007}, volume={26}, pages={527-541} }