Timestamp Temporal Logic (TTL) for Testing the Timing of Cyber-Physical Systems

  title={Timestamp Temporal Logic (TTL) for Testing the Timing of Cyber-Physical Systems},
  author={Mohammadreza Mehrabian and Mohammad Khayatian and Aviral Shrivastava and John C. Eidson and Patricia Derler and Hugo A. Andrade and Ya-Shian Li-Baboud and Edward R. Griffor and Marc A. Weiss and Kevin B. Stanton},
  journal={ACM Transactions on Embedded Computing Systems (TECS)},
  pages={1 - 20}
In order to test the performance and verify the correctness of Cyber-Physical Systems (CPS), the timing constraints on the system behavior must be met. Signal Temporal Logic (STL) can efficiently and succinctly capture the timing constraints of a given system model. However, many timing constraints on CPS are more naturally expressed in terms of events on signals. While it is possible to specify event-based timing constraints in STL, such statements can quickly become long and arcane in even… 

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