Timed verification of the SPSMALL memory !

  title={Timed verification of the SPSMALL memory !},
  author={Manuel Baclet and Remy Chevallier},
The aim of the paper is to verify a small synchronous memory component with the real-time model checker Uppaal, taking into account the electrical propagation delays through gates and along wires. 

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Do standardized embedded IP transistor view exists for SoC IP integration

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Uppaal in a nutshell

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