Timed state space exploration using POSETs

Abstract

| This paper presents a new timing analysis algorithm for eecient state space exploration during the synthesis of timed circuits or the veriication of timed systems. The source of the computational complexity in the synthesis or veriication of a timed system is in nding the reachable timed state space. We introduce a new algorithm which utilizes geometric… (More)
DOI: 10.1109/43.845076

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