Time-to-digital converter for RF frequency synthesis in 90 nm CMOS

@article{Staszewski2005TimetodigitalCF,
  title={Time-to-digital converter for RF frequency synthesis in 90 nm CMOS},
  author={R. B. Staszewski and S. K. Vemulapalli and Prashanth Vallur and J. L. Wallberg and P. T. Balsara},
  journal={2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers},
  year={2005},
  pages={473-476}
}
We propose and demonstrate a 20 ps time-to-digital converter (TDC) in 90 nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital PLL for a fully-compliant GSM transceiver. The TDC core is based on a pseudo-differential digital architecture that makes it insensitive to NMOS and PMOS mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self… CONTINUE READING
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