Time-space energy consumption modeling of dynamic reconfigurable coarse-grain array processor datapath for wireless applications


The power consumption is a key aspect when designing a handheld device. Even when cycle accurate instruction set simulators for the ASIPs used in SDRs are existing to evaluate the performance of given mapping, the power consumption is evaluated only in the later phase during gate-level simulation. In this paper we propose an automatic way how to obtain… (More)


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