Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS

Abstract

This paper presents a 5GS/s 8-bit 40-way time-interleaved SAR ADC fabricated in 65nm CMOS. Two-level hierarchical interleaving is employed, resulting in 4 sub-ADCs each operating at 1.25GS/s at the topmost level with front-end track and hold samplers. The sub-ADCs use capacitive C-2C DACs to minimize the input capacitance and area. A novel background timing… (More)
DOI: 10.1109/ESSCIRC.2014.6942058

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@article{Wang2014TimeIC, title={Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS}, author={Luke Wang and Qiwei Wang and Anthony Chan Carusone}, journal={ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)}, year={2014}, pages={207-210} }