Time and Power optimizations in FPGA-based architectures for polyphase channelizers

Abstract

This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks required for spectral shaping and for an M-channel channelizer… (More)
DOI: 10.1109/ACSSC.2011.6190142

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Cite this paper

@article{Awan2011TimeAP, title={Time and Power optimizations in FPGA-based architectures for polyphase channelizers}, author={Mehmood-ur-Rehman Awan and Fred Harris and Peter Koch}, journal={2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)}, year={2011}, pages={914-918} }