Low-power asymmetric multi-core processors (AMPs) are nowadays present in a wide variety of mobile and hand-held devices, and have attracted a lot of attention due to their appealing energy efficiency. However, these processors contain cores with different performance capabilities asking for solutions specifically tailored to exploit all their potential. In this paper, we provide two architecture-aware parallel solutions of two new technologies introduced in the HEVC standard to support high-level parallelism, namely wave-front parallel processing (WPP) and Tiles. These solutions leverage thread migration to keep the most powerful cores of the AMP busy processing the most priority tasks. The experimental results of an HEVC decoder running on an ARM big.LITTLE AMP demonstrate the benefits that can be obtained when the asymmetry of the target architecture is taken into account to carry out scheduling decisions.