Tile/line access cache memory based on a multi-level Z-order tiling data layout

@article{Wang2018TilelineAC,
  title={Tile/line access cache memory based on a multi-level Z-order tiling data layout},
  author={BaoKang Wang and Yuki Fukazawa and Toshio Kondo and Takahiro Sasaki},
  journal={Concurrency and Computation: Practice and Experience},
  year={2018},
  volume={30}
}

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