Tight Bounds on Expected Time to Add Correctly and Add Mostly Correctly


We consider the problem of adding two n-bit numbers which are chosen independently and uniformly at random where the adder is a circuit of AND, OR, and NOT gates of fan-in two. The fastest currently known worst-case adder has running time logn +O( p logn) [Khr]. We rst present a circuit which adds at least 1 fraction of pairs of numbers correctly and has… (More)
DOI: 10.1016/0020-0190(94)90031-0


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