Thru-silicon vias for 3D WLP

@article{Savastionk2000ThrusiliconVF,
  title={Thru-silicon vias for 3D WLP},
  author={S. Savastionk and Oleg Siniaguine and Ed Korczynski},
  journal={Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507)},
  year={2000},
  pages={206-207}
}
  • S. Savastionk, O. Siniaguine, E. Korczynski
  • Published 6 March 2000
  • Business, Engineering
  • Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507)
Thru-Silicon designs and manufacturing process flows are introduced as a means to produce 3D wafer level packaging solutions. Standard silicon IC manufacturing unit-processes must be combined into robust process-flows to allow for the rapid deployment of wafer-level packaging throughout the industry. 
Including inductance in static timing analysis
TLDR
Analytical expressions are derived for effective load capacitances of RLC interconnects to accurately estimate both the propagation delay and transition time at the output of a CMOS gate to accommodate inductance.
Including inductance in static timing analysis
In this paper analytical expressions are derived for effective load capacitances of RLC interconnects to accurately estimate both the propagation delay and transition time at the output of a CMOS