Thru-silicon vias for 3D WLP
@article{Savastionk2000ThrusiliconVF, title={Thru-silicon vias for 3D WLP}, author={S. Savastionk and O. Siniaguine and E. Korczynski}, journal={Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507)}, year={2000}, pages={206-207} }
Thru-Silicon designs and manufacturing process flows are introduced as a means to produce 3D wafer level packaging solutions. Standard silicon IC manufacturing unit-processes must be combined into robust process-flows to allow for the rapid deployment of wafer-level packaging throughout the industry.
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