• DOI:10.1109/ISAPM.2000.869271
Corpus ID: 110397071

Thru-silicon vias for 3D WLP

@article{Savastionk2000ThrusiliconVF,
  title={Thru-silicon vias for 3D WLP},
  author={S. Savastionk and O. Siniaguine and E. Korczynski},
  journal={Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507)},
  year={2000},
  pages={206-207}
}

S. Savastionk, O. Siniaguine, E. Korczynski

Published 2000

Materials Science

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507)

View on IEEE

doi.org

Save to Library

Create Alert

Cite

Launch Research Feed

Thru-Silicon designs and manufacturing process flows are introduced as a means to produce 3D wafer level packaging solutions. Standard silicon IC manufacturing unit-processes must be combined into robust process-flows to allow for the rapid deployment of wafer-level packaging throughout the industry.