Partial reversibility is an underexplored avenue for balancing high computational throughput and low power dissipation in nanocomputing systems. In this work we study the throughput-dissipation tradeoff in a partially reversible 32bit MIPS ALU implemented in quantum cellular automata and clocked via the “pipelined Bennett clocking” strategy recently introduced by Ottavi and co-workers. Fundamental upper bounds on the computational power efficiency (operations per Watt second) – as limited by dissipation from logical irreversibility – are evaluated as a function of the number of pipeline zones used in the ALU clocking, and are compared to corresponding results for pure Bennett clocking (which maximizes reversibility) and standard Landauer clocking (which maximizes throughput). Pipelined Bennett clocking is shown to offer both significant power efficiency advantages over Landauer clocking and throughput advantages over pure Bennett clocking for ALUs with small numbers of pipeline zones. These efficiency advantages are, however, lost for larger numbers of pipeline zones, where Landauer clocking provides superior efficiency and throughput. The observed throughput-dissipation tradeoff is explained in terms of relative communication and computation costs in pipelined Bennett clocking. Implications for partially reversible circuit design are briefly discussed.