Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding

@article{Tanaka2009ThroughSiliconVI,
  title={Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding},
  author={Nobuo Tanaka and Y. Yoshimura and Michihiro Kawashita and Tomohiro Uematsu and Chuichi Miyazaki and Nenad Toma and Kazuma Hanada and Masanori Nakanishi and Takayuki Naito and Tsuneomi Kikuchi and Teruyuki Akazawa},
  journal={IEEE Transactions on Advanced Packaging},
  year={2009},
  volume={32},
  pages={746-753}
}
One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use… CONTINUE READING

Citations

Publications citing this paper.
SHOWING 1-8 OF 8 CITATIONS

Nanobonding Technology Toward Electronic, Fluidic, and Photonic Systems Integration

  • IEEE Journal of Selected Topics in Quantum Electronics
  • 2011
VIEW 4 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Double-Shielded Interposer With Highly Doped Layers for High-Speed Signal Propagation

  • IEEE Transactions on Electromagnetic Compatibility
  • 2014
VIEW 1 EXCERPT
CITES BACKGROUND

Efficient Wafer-Level Edge-Tracing Technique for 3-D Interconnection of Stacked Die

  • IEEE Transactions on Components, Packaging and Manufacturing Technology
  • 2012

Novel sidewall interconnection using perpendicular circuit die with non-solder bumps for 3D chip stack

  • 2012 IEEE 62nd Electronic Components and Technology Conference
  • 2012
VIEW 1 EXCERPT
CITES METHODS

References

Publications referenced by this paper.
SHOWING 1-8 OF 8 REFERENCES

A CMOS-compatible process for fabricating electrical through-vias in silicon

  • 56th Electronic Components and Technology Conference 2006
  • 2006
VIEW 1 EXCERPT

Fabrication and electrical characterization of 3D vertical interconnects

  • 56th Electronic Components and Technology Conference 2006
  • 2006
VIEW 1 EXCERPT

Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding

  • 56th Electronic Components and Technology Conference 2006
  • 2006
VIEW 1 EXCERPT

Optimization for chip stack in 3-D packaging

  • IEEE Transactions on Advanced Packaging
  • 2005
VIEW 1 EXCERPT

Ultra-Thin 3D-Stacked SIP Formed using Room-Temperature Bonding between Stacked Chips

  • Proceedings Electronic Components and Technology, 2005. ECTC '05.
  • 2005
VIEW 1 EXCERPT

Current status of research and development for three dementional stacking technology

K. Takahashi
  • Jpn J. Appl. Phys., vol. 40, pp. 3032–3037, 2001.
  • 2001
VIEW 2 EXCERPTS

Feasibility of surface activated bonding for ultra-fine pitch interconnection-a new concept of bump-less direct bonding for system level packaging

  • 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)
  • 2000
VIEW 1 EXCERPT