Through Silicon Via Reliability

@article{Cassidy2012ThroughSV,
  title={Through Silicon Via Reliability},
  author={C. Cassidy and Jochen Kraft and Sara Carniello and Frederic Roger and Hajdin Ceric and Anderson Pires Singulani and Erasmus Langer and Franz Schrank},
  journal={IEEE Transactions on Device and Materials Reliability},
  year={2012},
  volume={12},
  pages={285-295}
}
Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage… CONTINUE READING
Highly Cited
This paper has 44 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 31 extracted citations

References

Publications referenced by this paper.
Showing 1-10 of 23 references

Passi - vation integrity investigations for through wafer interconnects

  • S. Carniello, F. Schrank, E. Wachmann
  • 2011

Vardaman, “3D TSV infrastructure: Challenges and opportunities,

  • E J.
  • Proc. ITC 3D Test Electron. Workshop Dig.,
  • 2011
1 Excerpt

and F

  • C. Cassidy, S. Watts, +5 authors J. Kraft
  • Schrank, “Product level screening of latent…
  • 2011

and J

  • R. Minixhofer, F. Roger, S. Carniello
  • M. Park, Two- and Three- Dimensional TCAD…
  • 2011

and M

  • J. Kraft, F. Schrank, +7 authors C. Schmidt
  • Petzold, “3D sensor application with open through…
  • 2011
3 Excerpts

Characterization and failure analysis of 3 D integrated semiconductor devices — Novel tools for fault isolation , target preparation and high resolution material analysis , ” in

  • M. Petzold Altmann, C. Schmidt, R. Salzer, C. Cassidy, P. Tesch
  • Proc . 36 th Int . Symp . Testing Failure Anal .
  • 2010

Characterization and failure analysis of 3D integrated semiconductor devices—Novel tools for fault isolation

  • F. Altmann, M. Petzold, C. Schmidt, R. Salzer, C. Cassidy, P. Tesch
  • target preparation and high resolution material…
  • 2010
1 Excerpt

Similar Papers

Loading similar papers…