Through Silicon Via Reliability

  title={Through Silicon Via Reliability},
  author={C. Cassidy and Jochen Kraft and Sara Carniello and Frederic Roger and Hajdin Ceric and Anderson Pires Singulani and Erasmus Langer and Franz Schrank},
  journal={IEEE Transactions on Device and Materials Reliability},
Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage… CONTINUE READING
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