Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs

@article{Lung2013ThroughSiliconVF,
  title={Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs},
  author={Chiao-Ling Lung and Yu-Shih Su and Hsih-Hsiu Huang and Yiyu Shi and Shih-Chieh Chang},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2013},
  volume={32},
  pages={1100-1109}
}
Clock network synthesis is one of the most important and challenging problems in 3-D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with minimum skew. While there are a few related works in literature, none consider the reliability of TSVs in a clock tree. Accordingly, the failure of any TSV in the clock tree yields a bad chip. The naive solution using double-TSV can alleviate the problem, but the significant area overhead renders it less practical… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-10 of 33 references

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

IEEE Journal of Solid-State Circuits • 2010
View 5 Excerpts
Highly Influenced

Clock tree synthesis with pre-bond testability for 3D stacked IC Designs

Design Automation Conference • 2010
View 4 Excerpts
Highly Influenced

Method and apparatus for providing through silicon via (TSV) redundancy

J. Kim, F. Wang, M. Nowak
United State Patent Application Publication, U.S. 2010/0295600A1, Nov. 2010. • 2010
View 5 Excerpts
Highly Influenced

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

2008 IEEE/ACM International Conference on Computer-Aided Design • 2008
View 4 Excerpts
Highly Influenced

High-frequency measurements of TSV failures

2012 IEEE 62nd Electronic Components and Technology Conference • 2012
View 1 Excerpt

TSV Redundancy: Architecture and Design Issues in 3-D IC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2012
View 2 Excerpts

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

IEEE Journal of Solid-State Circuits • 2011
View 1 Excerpt

Fault-tolerant 3D clock network

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) • 2011
View 2 Excerpts

Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2011
View 3 Excerpts

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