Threshold-alterable Si-gate MOS devices
@article{Chen1977ThresholdalterableSM,
title={Threshold-alterable Si-gate MOS devices},
author={P.C.Y. Chen},
journal={IEEE Transactions on Electron Devices},
year={1977},
volume={24},
pages={584-586}
}An electrically threshold-alterable n-channel MOS device with polysilicon gate is experimentally realized by employing a polysilicon-oxynitride-nitride-oxide-silicon (SONOS) structure. Because of several high-temperature processing steps after the nitride deposition, it was found necessary to increase the thin-oxide thickness of the SONOS devices in order to achieve better charge retentivity. It has been shown that the SONOS device can be used in MOS integrated circuits. Some memory and…
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References
SHOWING 1-10 OF 10 REFERENCES
The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device
- Engineering
- 1967
A memory element has been developed that has the structure of a typical silicon planar p-channel enhancement insulated-gate field-effect transistor (IGFET). The information is stored by setting the…
Interfacial dopants for dual-dielectric, charge-storage cells
- Engineering
- 1974
When a suitable interfacial dopant, such as W, is introduced at the interface between the dielectrics of a DDC cell, the write-erase characteristics of the cell are greatly improved. The useful range…
Switching and storage characteristics of MIS memory transistors
- Physics
- 1968
Transistors with memory hawe been constructed in the form of MIS field-effect transistors in which the gate insulator consists of a double layer. Closest to the silicon is a silicon dioxide layer, no…
A high-density, read/write, nonvolatile charge-addressed memory
- Computer Science1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
- 1976
A high density, read/write, 16K-bit (0.5 mil2/bit) non-volatile charge-addressed memory with TTL compatibility and full decoding with crosspoint geometry and address-decode features is described.
Processing of non - volatile memories
- J . Electrochem . Soc .
The drainsource protected MNOS memory device and memorv endurance
- J . Electrochem Soc .