Three generations of asynchronous microprocessors

@article{Martin2003ThreeGO,
  title={Three generations of asynchronous microprocessors},
  author={Alain J. Martin and Mika Nystr{\"o}m and Catherine G. Wong},
  journal={IEEE Design \& Test of Computers},
  year={2003},
  volume={20},
  pages={9-17}
}
We trace the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. We describe the control aspects of the evolving circuit styles. We describe these three generations of asynchronous microprocessors (Caltech asynchronous processors, MiniMIPS and Lutonium) and the corresponding circuit families and design methods. The… 

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References

SHOWING 1-10 OF 21 REFERENCES
The design of an asynchronous microprocessor
TLDR
This is the first entirely asynchronous microprocessor ever built and it is quite aware that asynchronous techniques may influence the computer architects in completely new ways that this first design is just starting to explore.
The design of an asynchronous MIPS R3000 microprocessor
TLDR
The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.
A Synthesis Method for Self-Timed VLSI Circuits
TLDR
With chip size reaching 1 million transistors, the need for high-level design of circuits becomes compelling and timing is the most-critical, since it is not only essential to the real-time behavior of a circuit, but also to its logical correctness if synchronous techniques are used.
The Lutonium: a sub-nanojoule asynchronous 8051 microcontroller
TLDR
The structure of a fine-grain pipeline optimized for Et/sup 2/ efficiency, some of the peripherals implementation, and the advantages of an asynchronous implementation of a deep-sleep mechanism are described.
AMULET2e: an asynchronous embedded controller
TLDR
An embedded system chip incorporating an enhanced asynchronous ARM core (AMULET2), a 4 Kbyte pipelined cache, a flexible memory interface and assorted programmable control functions, and innovative features that exploit its asynchronous operation to advantage in power-sensitive applications are described.
An asynchronous low-power 80C51 microcontroller
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 /spl mu/ CMOS process and it shows a power advantage of a factor 4 compared to a
Synthesis of Asynchronous VLSI Circuits
TLDR
This work proposes a concurrent programming approach to digital VLSI design, where a digital circuit is the implementation of a concurrent algorithm, and the circuit to be designed is first implemented as a concurrent program that fulfills the logical specification of the circuit.
ET 2 : a metric for time and energy efficiency of computation
TLDR
An efficiency metric for VLSI computation that includes energy is investigated and an approximation for Etn (for arbitrary n) of an optimally sized system that can be computed without actually sizing the transistors is derived; it is proved that when multiple, adjustable supply voltages are allowed, the optimal Et2 for the sequential composition of components is achieved when the supply voltage is adjusted so that the components consume equal power.
TITAC-2 : A 32-bit scalable-delay-insensitive microprocessor
TLDR
This is a list of notable people from Japan who have contributed to the development of microelectronics in the past 50 years.
Pénzes, “Et2: A Metric for Time and Energy Efficiency of Computation,
  • PowerAware Computing,
  • 2002
...
...