Three-dimensional place and route for FPGAs


We present timing-driven partitioning and simulated annealing based placement algorithms together with a detailed routing tool for 3D FPGA integration. The circuit is first divided into layers with limited number of inter-layer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. Experimental results show on average a total decrease of 21% in wire-length and 24% in delay, can be achieved over traditional 2D chips, when five layers are used in 3D integration.

DOI: 10.1145/1120725.1121015

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@article{Ababei2005ThreedimensionalPA, title={Three-dimensional place and route for FPGAs}, author={Cristinel Ababei and Hushrav Mogal and Kia Bazargan}, journal={Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.}, year={2005}, volume={2}, pages={773-778 Vol. 2} }