Three-dimensional integrated circuits

  title={Three-dimensional integrated circuits},
  author={Anna W. Topol and Douglas C. La Tulipe and Leathen Shi and David J. Frank and Kerry Bernstein and Steven E. Steen and Arvind Kumar and Gilbert U. Singco and Albert M. Young and Kathryn W. Guarini and Meikei Ieong},
  journal={IBM J. Res. Dev.},
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits… Expand
Three-dimensional silicon integration
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3D silicon integration
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We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance betweenExpand
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The four-layer-stacked master slice is proposed as a system application for 3-D ICs. The master slice consists of a programmable logic array for logic circuits, a CMOS gate array for I/O interfaceExpand
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A three-dimensional (3-D) CMOS integrated circuit was fabricated based on the conventional CMOS SOI technology. The first layer of transistors was formed on the SOI. The second layer of transistorsExpand
Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)
  • A. Rahman, R. Reif
  • Materials Science
  • Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)
  • 2001
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