Three dimensional ICs, having four stacked active device layers

@article{Kunio1989ThreeDI,
  title={Three dimensional ICs, having four stacked active device layers},
  author={Takemitsu Kunio and Ken Oyama and Yoshihiro Hayashi and M. Morimoto},
  journal={International Technical Digest on Electron Devices Meeting},
  year={1989},
  pages={837-840}
}
The four-layer-stacked master slice is proposed as a system application for 3-D ICs. The master slice consists of a programmable logic array for logic circuits, a CMOS gate array for I/O interface buffer circuits, and a CMOS SRAM. Fabrication technologies for the four-layer-stacked 3-D IC are described. Laser beam recrystallization was carried out for the formation of three SOI (silicon-on-insulator) layers in the 3-D IC. Recrystallization without cracks in both SOI and vertical isolation… 

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