Three dimensional IC for high performance image signal processor

  title={Three dimensional IC for high performance image signal processor},
  author={T. Nishimura and Y. Inoue and K. Sugahara and S. Kusunoki and T. Kumamoto and S. Nakagawa and M. Nakaya and Y. Horiba and Y. Akasaka},
  journal={1987 International Electron Devices Meeting},
  • T. Nishimura, Y. Inoue, +6 authors Y. Akasaka
  • Published 1987
  • Computer Science
  • 1987 International Electron Devices Meeting
  • The three-dimensional (3-D) image processing test IC designed with parallel processing architecture is fabricated. The device consists of 5-by-5 array of photosensors, 2-bit CMOS A-to-D converters, 40 arithmetic logic units (ALU) and shiftregisters arranged in a 3-layer structure. The total operation from photosensor on top layer to ALU on bottom layer is confirmed, and it is also demonstrated the feasibility of very high speed system operation with the implement of parallel processing. This… CONTINUE READING
    43 Citations

    Figures, Tables, and Topics from this paper

    Real-Time Focal-Plane Array Image Processor
    • 18
    Single-chip image sensors with a digital processor array
    • 24
    Architectures For Focal Plane Image Processing
    • 57
    • PDF
    3 D-stacking architecture for low-noise high-speed image sensors
    • 1
    • PDF
    PASIC: A processor-A/D converter-sensor integrated circuit
    • 27
    An SOI/CMOS flash A/D converter
    • 1
    Three dimensional ICs, having four stacked active device layers
    • 63
    • Highly Influenced
    Monolithic 3-D Integration of SRAM and Image Sensor Using Two Layers of Single-Grain Silicon
    • 19
    Generic functions for on-chip vision
    • B. Zavidovique, T. Bernard
    • Computer Science
    • Proceedings., 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition,
    • 1992
    • 12