Three dimensional IC for high performance image signal processor

@article{Nishimura1987ThreeDI,
  title={Three dimensional IC for high performance image signal processor},
  author={Tetsuya Nishimura and Y. Inoue and Kazuyuki Sugahara and Shigeru Kusunoki and T. Kumamoto and Shinichi Nakagawa and Masao Nakaya and Yasutaka Horiba and Yuzo Akasaka},
  journal={1987 International Electron Devices Meeting},
  year={1987},
  pages={111-114}
}
The three-dimensional (3-D) image processing test IC designed with parallel processing architecture is fabricated. The device consists of 5-by-5 array of photosensors, 2-bit CMOS A-to-D converters, 40 arithmetic logic units (ALU) and shiftregisters arranged in a 3-layer structure. The total operation from photosensor on top layer to ALU on bottom layer is confirmed, and it is also demonstrated the feasibility of very high speed system operation with the implement of parallel processing. This… 

Figures and Tables from this paper

Real-Time Focal-Plane Array Image Processor
TLDR
A focal-plane-array chip designed for real-time, general-purpose, image preprocessing is reported, and the simulation of an edge detection algorithm implemented by the chip is presented.
Automated Inspection and High . . Speed Vision Architectures III
TLDR
A focal-plane-array chip designed for real-time, general-purpose, image preprocessing, and the simulation of an edge detection algorithm implemented by the chip is presented.
Single-chip image sensors with a digital processor array
TLDR
The architectures, implementation and applications of two smart sensors, LAPP and PASIC, are described, which provide fast, compact and economic solutions for tasks such as industrial inspection, optical character recognition and robot vision.
Architectures For Focal Plane Image Processing
TLDR
The potential of on-chip read/write analog frame memory for image transformation and frame-to-frame processing is discussed and a new pipelined vector pixel processor architecture for medium density infrared staring focal plane arrays is described.
3 D-stacking architecture for low-noise high-speed image sensors
In this paper, architectures for low-noise high-speed image sensors based on 3D stacking technology are discussed. Effectiveness of the 3D-stacking technology for low-noise high-speed image sensors
PASIC: A processor-A/D converter-sensor integrated circuit
TLDR
The design of an integrated smart sensor called PASIC is described, to integrate a 2-D image-sensor array with a linear A/D converter array and a linear processor array in a single chip.
An SOI/CMOS flash A/D converter
An A/D conversion is an indispensable function in three-dimensional(S-D) integrated circuits when 3-D technology is applied to construct the analog-digital combined system, for example, an
Three dimensional ICs, having four stacked active device layers
The four-layer-stacked master slice is proposed as a system application for 3-D ICs. The master slice consists of a programmable logic array for logic circuits, a CMOS gate array for I/O interface
Monolithic 3-D Integration of SRAM and Image Sensor Using Two Layers of Single-Grain Silicon
In this paper, we report monolithic integration of two single-grain silicon layers for static random access memory (SRAM) and image sensor applications. A 12 × 28 silicon lateral photodiode array
Technology and Devices for Silicon Based Three-Dimensional Circuits
The recent success in the development of three-dimensional circuits has demonstrated that stacked device structures might become an alternative for further increase of integration density and
...
...