Three dimensional IC for high performance image signal processor

@article{Nishimura1987ThreeDI,
  title={Three dimensional IC for high performance image signal processor},
  author={Tetsuya Nishimura and Y. Inoue and Kazuyuki Sugahara and Shigeru Kusunoki and T. Kumamoto and Shinichi Nakagawa and Masao Nakaya and Yasutaka Horiba and Yuzo Akasaka},
  journal={1987 International Electron Devices Meeting},
  year={1987},
  pages={111-114}
}
The three-dimensional (3-D) image processing test IC designed with parallel processing architecture is fabricated. The device consists of 5-by-5 array of photosensors, 2-bit CMOS A-to-D converters, 40 arithmetic logic units (ALU) and shiftregisters arranged in a 3-layer structure. The total operation from photosensor on top layer to ALU on bottom layer is confirmed, and it is also demonstrated the feasibility of very high speed system operation with the implement of parallel processing. This… 
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