Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

@article{Koyanagi2006ThreeDimensionalIT,
  title={Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections},
  author={Mitsumasa Koyanagi and Tetsuya Nakamura and Yuji Yamada and Hiroyuki Kikuchi and Takafumi Fukushima and Tetsu Tanaka and Hiroyuki Kurino},
  journal={IEEE Transactions on Electron Devices},
  year={2006},
  volume={53},
  pages={2799-2808}
}
A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the… CONTINUE READING
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