Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs

@article{Patti2006ThreeDimensionalIC,
  title={Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs},
  author={Robert S. Patti},
  journal={Proceedings of the IEEE},
  year={2006},
  volume={94},
  pages={1214-1224}
}
Three-dimensional integrated circuits (3-D ICs) offer significant improvements over two-dimensional circuits, and promise a solution to the severe problems that are being, and will be, encountered as monolithic process geometries are reduced to below 65 nm. Several methods associated with the fabrication of 3-D ICs are discussed in this paper, and the techniques developed by Tezzaron Semiconductor Corp., are described in detail. Four successful 3-D ICs are described, along with the anticipated… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-10 of 17 references

BA new super smart stack technology for 3-D LSIs,[ presented at the RTI Int

M. Koyanagi
Technology Venture Forum, Tempe, AZ, • 2005
View 2 Excerpts

BIntegration challenges of 3-D bonded structures,[ presented at the TechVenture Preconf

S. Pozder
2005
View 2 Excerpts

BSolid face-to-face goes productive at Infineon,[ presented at the SEMICON Europa

H. Huebner
2005
View 2 Excerpts

BWafer-stacked package technology for high-performance system,[ presented at the RTI

K. Lee
Int. Technology Venture Forum, Tempe, AZ, • 2005
View 2 Excerpts

Nov.). BRips in the road map,

E. Sperling, J. Chappell
Electron. News. [Online]. Available: http://www.reedelectronics.com/electronicnews/article/ CA6253270 • 2005
View 2 Excerpts

and G

B. Rajendran, D. J. Witte, +3 authors R. L. DeLeon
S. Tompa, BCMOS transistor processing compatible with monolithic 3-D integration,[ in Proc. VLSI Interconnection Conf. (VMIC) • 2005
View 2 Excerpts

and R

F. Nicklaus, J. J. McMahon, +3 authors T. S. Cale
J. Gutmann, BWafer-level 3-D integration technology platforms for IC’s and MEMS,[ in Proc. VLSI Interconnection Conf. (VMIC) • 2005
View 2 Excerpts

and S

V. Dunton, T. Chen, M. Konevecki, U. Raghuram
Sivaram, BZias: Vertical wires in 3-D memory devices,[ in Proc. VLSI Interconnection Conf. (VMIC) • 2005
View 2 Excerpts

B3-dimensional ICs: Motivation

K. Saraswat
performance analysis and technology,[ pre- sented at the 3D Technology, Modeling, and Process Symp., Burlingame, CA • 2004
View 2 Excerpts

B3D IC technology: Capabilities and applications,[ presented at the RTI

K. Guarini
Int. Technology Venture Forum, • 2004
View 2 Excerpts

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