• Corpus ID: 29105721

This technology allows stacked silicon chips to interconnect through direct contact to provide high-speed signal processing and improved photo detection for image sensing.

@inproceedings{Motoyoshi2009ThisTA,
  title={This technology allows stacked silicon chips to interconnect through direct contact to provide high-speed signal processing and improved photo detection for image sensing.},
  author={Makoto Motoyoshi},
  year={2009}
}
Recently, the development of three-dimensional large-scale integration (3D-LSI) has been accelerated. Its stage has changed from the research level or limited production level to the investigation level with a view to mass production (1)-(10). The 3D-LSI using through-silicon via (TSV) has the simplest structure and is expected to realize a high-performance, high- functionality, and high-density LSI cube. This paper describes the current and future 3D-LSI technologies with TSV. 

References

SHOWING 1-10 OF 33 REFERENCES
Three-Dimensional Integration Technology for Advanced Focal Planes
We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale
Future system-on-silicon LSI chips
TLDR
In this work, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using a new three-dimensional integration technology to overcome future wiring connectivity crises.
Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology
  • V. Suntharalingam, R. Berger, D. Young
  • Physics, Engineering
    ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
  • 2005
A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method.
Intelligent image sensor chip with three dimensional structure
  • H. Kurino, K. Lee, M. Koyanagi
  • Engineering
    International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
  • 1999
A new three-dimensional (3D) integration technology based on wafer bonding technique has been proposed for intelligent image sensor chip with 3D stacked structure. We have developed key technologies
A 0.14mW/Gbps high-density capacitive interface for 3D system integration
TLDR
High bit-rate, reduced power consumption and electrode area down to 8/spl times/8/spl mu/m/sup 2/ enable the implementation of highly parallel pipelined interfaces for inter-chip communication, with an aggregate consumption of about 0.14mW/Gbps.
Three-dimensional shared memory fabricated using wafer stacking technology
TLDR
It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.
Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions
This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
B Megapixel CMOS image sensor fabricated in three - dimensional integrated circuit technology
  • ISSCC Dig . Tech . Papers
  • 2007
BBridging the gap to TSV,
  • Proc. Conf. 3-D Architect. Semiconduct. Integr. Packag.,
  • 2007
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