Thermo-mechanical reliability of 3-D ICs containing through silicon vias

@article{Lu2009ThermomechanicalRO,
  title={Thermo-mechanical reliability of 3-D ICs containing through silicon vias},
  author={Kuan H. Lu and Xuefeng Zhang and Suk-Kyu Ryu and Jay Im and Rui Huang and Paul S. Ho},
  journal={2009 59th Electronic Components and Technology Conference},
  year={2009},
  pages={630-634}
}
In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) raise serious reliability issues such as Si cracking and performance degradation of devices. In this study, the thermo-mechanical reliability of 3-D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. FEA simulation demonstrated that the thermal stresses in silicon decrease as a function of distance from an isolated TSV and increase with the TSV… CONTINUE READING
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